The following references are useful as starting points for understanding the field of magnetoelectronic logic circuits:    Mark Johnson, U.S. Pat. No. 6,140,838, “High Density and High Speed Magneto-electronic Logic Family” (October 2000).    Mark Johnson, B. R. Bennett, P. R. Hammar and M. M. Miller, “Magnetoelectronic Latching Boolean Gate,” Solid-State Electronics 44, 1099 (2000).    H. Meng, J. Wang and J. -P. Wang, “A spintronics full adder for magnetic CPU,” IEEE Electron. Device Lett., vol. 26 (6), pp. 360-362, (2005).    Tae-wan Kim et al., U.S. Pat. No. 7,439,770 B2, “Magnetic Tunneling Junction Based Logic Circuits and Methods of Operating Same,” (January 2008).    Mark Johnson, “Magnetic Logic: Fundamentals, Devices, and Applications,” Wiley Encyclopedia of Electrical and Electronics Engineering, ed. John Webster, (John Wiley and Sons, Inc., Hoboken, N.J., 2015).    Neal Berger and Mourad El Baraji, U.S. Pat. No. 8,218,349 B2, “Non-volatile Logic Devices Using Magnetic Tunnel Junctions,” (July 2012).    Lew G. Chua-Eoan et al., U.S. Pat. No. 8,295,082 B2, “Gate level reconfigurable magnetic logic” (October 2012).    Mark Johnson, U.S. Pat. No. 9,024,656,“Nonvolatile Logic Circuit Architecture and Method of Operation,” (May, 2015).
The present application involves magnetoelectronic cells used for Boolean logic and Memory applications. The use of magnetoelectronic devices for memory and Boolean logic applications has been described in the art for more than two decades. Early applications for nonvolatile integrated memory used anisotropic magnetoresistive devices in a block-addressable random access memory (RAM) architecture. U.S. Pat. No. 5,565,695 (“Magnetic spin transistor hybrid circuit element,” 1996), by the inventor described a memory cell composed of a magnetoelectronic device (spin transistor) and a field effect transistor (FET) used to isolate the cell from a two dimensional array of cells. This cell was then used in a bit-addressable magnetic RAM (MRAM) architecture. U.S. Pat. No. 5,629,549 (“Magnetic spin transistor device, logic gate & method of operation,” 1997), by the inventor, described the use of a magnetoelectronic device (spin transistor) for simple Boolean logic operations such as AND, OR, NAND and NOR. A similar description was published by the inventor as “The all-metal spin transistor,” I.E.E.E. Spectrum Magazine 31 (5), 47 (1994).
U.S. Pat. No. 6,140,838 (“High density and high speed magneto-electronic logic family,” 2000), by the inventor, described the response of the magnetization orientation of a patterned ferromagnetic element to magnetic field pulses as the result of Boolean logic operations. The ferromagnetic film therefore performed as a Boolean logic gate. The field pulses were associated with pulses of current applied to inductively coupled input wires. A ferromagnetic element having 3 input terminals was described. Terminals A and B were used for binary data input. A pulse applied to terminal C would control the function of the gate. For control pulses of logical 0 or 1, the gate could be configured to perform a Boolean AND or OR operation. An alternative operation performed NAND or NOR operations. The ferromagnetic film was incorporated as part of a magnetoelectronic device. Readout of the result of the operation involved activating the magnetoelectronic device. These ideas were published as “Magnetoelectronic Latching Boolean Gate,” Solid-State Electronics 44, 1099 (2000), where the ferromagnetic film was incorporated as part of a Hybrid Hall Effect (HHE) device. Implementation of the HHE device for this kind of reconfigurable logic was described in patent '838. This patent generalized the reconfigurable logic idea to the case where the ferromagnetic film is incorporated in a generic magnetoelectronic device.
The article “A spintronics full adder for magnetic CPU” (IEEE Electron. Device Lett., vol. 26 (6), pp. 360-362, 2005) by H. Meng, J. Wang and J. -P. Wang, describes the same Boolean operations described in '838 for the case where a ferromagnetic film with three inputs is incorporated in a magnetic tunnel junction (MTJ). The MTJ has three input terminals, A, B and C. Instead of providing inputs in the form of a locally applied magnetic field, the inputs to the MTJ use spin polarized current pulses in the spin torque transfer (STT) technique. The inputs are analogous and the spin polarized current pulses can be thought of as providing an effective magnetic field that operates on the magnetization orientation. In U.S. Pat. No. 7,439,770 B2 (2008), inventors Tae-wan Kim et al. describe the same cell and reconfigurable process presented in the article by Meng et al.
In “Magnetic Logic: Fundamentals, Devices, and Applications,” Wiley Encyclopedia of Electrical and Electronics Engineering, ed. John Webster, (John Wiley and Sons, Inc., Hoboken, N.J., 2015), the inventor describes a variation of the STT input mechanism in which the STT current is driven from a ferromagnetic source layer to a ferromagnetic free layer, and the free layer is incorporated in a magnetoelectronic device such as an MTJ. The resulting device has three STT inputs and performs as a reconfigurable Boolean logic gate.
Patent '838 also disclosed the invention of a simple composite cell composed of a magnetoelectronic device and a simple CMOS buffer amplifier. The specific case where the magnetoelectronic device is a HHE device was used. Digital logic processing typically involves multiple steps during which the output of one gate is used as the input to one or more subsequent gates. The composite cell has the advantage that it has CMOS output levels (for both LOW and HIGH) and fanout to subsequent logic gates (cells) in a chain of cells is readily achieved. The composite cell also can be used as nonvolatile memory for occasions when one or several data values must be stored, but a full 2-dimensional RAM array is not needed.
In U.S. Pat. No. 8,295,082 B2 (2012), Chua-Eoan et al. describe a reconfigurable composite logic cell. The basic cell is composed of 4 MTJs and 2 CMOS sensor circuits. The cell can be configured to perform the four basic Boolean operations, AND, OR, NAND and NOR. In the first step, each MTJ is individually “preset” by an input value of binary 0 or 1. In the second step, each MTJ receives one of four inputs: A, bar A, B and bar B. These inputs determine the output states of the 4 MTJs and the results are stored in a nonvolatile way. To read out a result, the output voltages of the MTJs are summed and transmitted to a first CMOS sensor circuit. This sensor circuit can be configured (by separate selection method) to have one of several different values of threshold voltage. The sensor circuit receives a selected threshold voltage and then gives output of a first logical signal that corresponds to the selection of one of two Boolean operations, e.g. AND or OR. The cell includes a second CMOS circuit that follows the first sensor circuit and is configured as a NOT gate (inverter). The result of a Boolean NAND or NOR operation is available at the output of the second CMOS circuit.
In U.S. Pat. No. 8,218,349 B2 (2012), Berger et al. present a register cell, described as an unbalanced flip-flop, composed of 2 MTJs integrated as circuit components inside the circuits of two CMOS inverters. The inventors then describe a shift register composed of a plurality of the register cells.
The incorporation of magnetoelectronic devices into more diverse domains is expected to increase in the near future. These devices offer a number of benefits, particularly in low power applications. For example, U.S. Pat. No. 9,024,656 by the present inventor (incorporated by reference herein) describes a system and method for performing low power logic operations. Whereas logic operation performed with traditional semiconductor technology relies on periodic synchronized pulses from a clock, operation of the low power technique uses individual pulses. In the former case, the logic system is constantly powered on. In the latter case, the quiescent state of the system is off. Power is applied only during the brief intervals when individual pulses are required. At all other times, the system draws no power. In '656, this novel kind of digital logic processing is called nonvolatile logic.
The invention described in '656 was motivated by the development of a novel device, the magnetic field controlled avalanche diode (MFCAD). The MFCAD is described in the article (Nature, 2013) and in U.S. Pat. No. 9,331,266 B2 (Joonyeon Chang, Mark Johnson et al., “Magnetic Field Controlled Reconfigurable Semiconductor Logic Device and Method for Controlling Same”). This device can behave as a nonvolatile reconfigurable Boolean logic cell. Patent '656 showed how the reconfigurable cell could be used for constructing logic building blocks, including as an Arithmetic Logic Unit (ALU) that performs binary logic operations. The patent then developed and presented an architecture for a nonvolatile digital logic and signal processing system. Dramatic power savings can be achieved because the normal operational state is “off.” When an operation is required, individual pulses are applied and, when the operation is complete, the results are stored in nonvolatile memory and the system returns to the quiescent, zero power condition.
The magnetic field controlled avalanche diode is a type of magnetoelectronic device where the output is an electric current. Most magnetoelectronic devices, for example the spin valve (SV) and the magnetic tunnel junction (MTJ), are magnetoresistors. They behave as variable resistors with bistable LOW and HIGH resistance values that are associated with binary 0 and 1, and thus can be considered as resistance-based elements. The resistance state is a function of the magnetization orientation of one (the free ferromagnetic layer) of two ferromagnetic layers in the SV or MTJ. The resistance state can be set (i.e. written) using a magnetic field to set a magnetization orientation state. For integrated devices, the magnetic field is associated with an electric write current. The write current may be applied through an inductively coupled write wire and produces a local magnetic field. Alternatively, the write current may be a spin polarized current injected directly into the ferromagnetic layer. The resistance state of the magnetoresistor then is sensed (i.e. read out) by applying a bias and measuring the resistance. The resistance state of the SV and MTJ is detected by electric transport properties associated with a spin polarized current that transits both ferromagnetic layers. Because magnetoresistors typically have a large resistance value, the bias is commonly a current and the output is read out is a voltage.
Thus, a typical magnetoelectronic device has current input and voltage output. These characteristics are ideal for nonvolatile memory but are problematic for logic. Digital logical processing requires multiple operations performed by different linked stages. One gate is linked to subsequent gates by fanout, with the output of one gate providing the input to one or more subsequent gates. Fanout requires that device output preferably should be a reliable and reproducible current source.
In the MFCAD, the channel of an avalanche diode has resistance values that depend on the orientation of an applied magnetic field. The diode typically is biased by a voltage and the output is a current that depends on the magnetic field. The MFCAD differs from the SV and MTJ in that detecting the output does not involve spin polarized current flowing in the channel of the device. For the integrated MFCAD, the external magnetic field is provided as a local fringe magnetic field near the ends of one or more patterned ferromagnetic elements. The magnetization states of the ferromagnetic elements, and therefore the locally applied fields, are bistable and nonvolatile.
Thus, the MFCAD is characterized as a device with bistable magnetization configurations that are set by applying an input write current (preferably an STT process) to patterned ferromagnetic elements in the MFCAD device cell. For read out, the diode channel is biased with a voltage to give an output in the form of a current, with bistable output current values that depend on the locally applied magnetic field, and therefore depend on the magnetization configuration of the ferromagnetic elements. As such, it is well suited for use in circuits with other MFCADs, or with other magnetoelectronic devices, where the input is required to be a current. A disadvantage of the MFCAD is that while it is a promising device, to date it is in an early stage of research and development and has not been commercialized.
The MFCAD has demonstrated basic reconfigurable functions. As described in (Nature, 2013) and '266, one embodiment of a single MFCAD reconfigurable cell can be reconfigured to perform an AND or OR function. A different embodiment can be reconfigured to perform a NAND or NOR function. The architecture described in '656 is general and works for an ALU that can be reconfigured to perform more than two Boolean functions. However, the example presented in '656 involved an ALU that could be reconfigured to perform two functions, the AND or OR function.